Skip to Main Content
This work reports on the considerations for building RF switches in deeply scaled CMOS. As demonstrator single pole single throw (SPST) switches in a standard 65 nm technology are designed and measured. Goal of this design is lowest insertion loss while achieving high power handling capability, linearity, and robustness. For the novel design of switch variant Dev 1 0.8dB of insertion loss, 30dBm of power handling and an input third order intermodulation intercept point (iIP3) of 48.8 dBm has been achieved at 1.8 GHz. High robustness is achieved by stacking 4 transistors. Isolation at 1.8 GHz is better than 22dB. For high power handling capability in off state a method is implemented to rise the DC voltage level at inner nodes of the switch. Thus the threshold voltage lowering in deeply scaled CMOS can be counteracted. The small and large signal behaviour of the switch is compared to conventional designs and benefits are proven.