Skip to Main Content
Silicon-on-insulator processes have the potential to realize high-quality factors in spiral inductors, but only if the loss mechanisms involved are clearly understood. Partially-depleted SOI (PD-SOI) processes must address losses in the semiconducting Silicon layer below the spiral inductor turns, even when high-resistivity substrates are employed. These losses are illustrated with a simplified lumped-element model and an array of inductors with different materials below is measured to confirm the theory. Q values achieved are up to 19 in the popular frequency range of 1 to 6 GHz without the use of expensive thick-metal in the process.