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Power gating is one of the most effective techniques to reduce the growing leakage power in the CMOS integrated circuits. However, during the turn on progress of the power gated circuits, ground bounce effect appears which will cause voltage fluctuations on the ground line within the chip through the parasitic parameters of package. In this paper, an analytical model is proposed to calculate the voltage fluctuations, and this model can be used to estimate the maximum and period of the fluctuations. A standard CMOS 90nm process is used to validate the model. Experimental results show that the errors of the period and maximum peak value of the voltage fluctuation are 10.18% and 9.98% on average compared with the SPICE simulation. The runtime could be greatly reduced.
Date of Conference: 12-16 Oct. 2011