Hardware friendly motion estimation algorithm and VLSI architecture for H.264/AVC coding

A simple and hardware-oriented motion estimation algorithm based on a 5×5 square shaped search pattern is presented in this paper. High performance VLSI architecture for this algorithm is proposed to increase the coding efficiency. Compared with full search algorithm, the algorithm can speed up 91% coding time with 0.15 dB Peak Signal to Noise Ratio (PSNR) loss and 4% bit rate increase on average. The frequency of the architecture is 200MHz with the 189k logic gates in SIMC 0.18 μm CMOS technology. This architecture has higher performance with less hardware cost than other several architectures and can be applied to high definition H.264/AVC coding in real time.