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Integrated Device–Fabric Explorations and Noise Mitigation in Nanoscale Fabrics

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5 Author(s)
Narayanan, P. ; Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA ; Kina, J. ; Panchapakeshan, P. ; Chi On Chui
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An integrated device-fabric methodology for evaluating and validating nanoscale computing fabrics is presented. The methodology integrates physical layer assumptions for materials and device structures with accurate 3-D simulations of device electrostatics and operations and circuit-level noise and cascading validations. Electrical characteristics of six different crossed nanowire field-effect transistors (xnwFETs) are simulated and current and capacitance data are obtained. Behavioral models incorporating device data are generated and used in fabric level simulations to evaluate noise implications of devices and sequencing schemes. Device characteristics are found to have different implications for logic “1” and logic “0” noise with faster devices being more (less) resilient to logic “1” (logic “0”) noise. A new noise resilient dynamic sequencing scheme is presented which isolates logic “0” noise events and prevents them from propagating to cascaded circuit stages, thereby enabling faster devices. Performance implications and optimizations for fabrics incorporating the new noise resilient scheme are discussed. The scheme is also analyzed and validated against an external noise source (power supply drooping). These results show that noise resilient nanofabrics can be designed through a combination of device engineering and fabric-level optimizations of the sequencing scheme. Performance optimizations and implications of device and physical layer assumptions on manufacturing are discussed.

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Nanotechnology, IEEE Transactions on  (Volume:11 ,  Issue: 4 )