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Fast multiply and divide for a VLSI floating-point unit

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4 Author(s)
Bose, B.K. ; Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720, USA ; Pei, L. ; Taylor, G.S. ; Patterson, D.A.

This paper presents the design of a fast and area-efficient multiply-divide unit used in building a VLSI floating-point processor (FPU), conforming to the IEEE standard 754. Details of the algorithms, implementation techniques and design tradeoffs are presented, The multiplier and divider are implemented in 2 micron CMOS technology with two layers of metal, and occupy 23 square mm (23% of the entire FPU). We expect to perform extended-precision multiplication and division in 1.1 and 2.8 microseconds, respectively.

Published in:

Computer Arithmetic (ARITH), 1987 IEEE 8th Symposium on

Date of Conference:

18-21 May 1987