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Design of a low-power high-speed CMOS frequency divider for WSN applications

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2 Author(s)
Sun Zhenhua ; Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China ; Li Zhiqun

A 5-GHz CMOS programmable frequency divider is presented in this paper, whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications. The divider has two blocks, a dual-modulus prescaler (DMP) integrating a frequency halving circuit, and a pulse-swallow counter. In the DMP, an improved phase switching technique is used to reduce the power consumption. Designed in 0.18-μm CMOS process, simulation shows that the divider can operate over a wide range of 1-6.5 GHz, consumes 7.7 mW from a single 1.8 V supply, and occupies a chip area of approximately 0.02 mm2.

Published in:

Communication Technology (ICCT), 2011 IEEE 13th International Conference on

Date of Conference:

25-28 Sept. 2011