A low power programmable gain amplifier with 70-dB control range in CMOS technology

This paper presents a low power programmable gain amplifier (PGA) for low intermediate frequency (IF) Zigbee transceiver applications in 0.18-µm CMOS process. The designed PGA uses ac coupling between the stages to avoid the amplification of DC offset. The post-simulations demonstrate the gain of the PGA can be varied linearly from 0 dB to 70 dB with a step size of 2 dB. The PGA can operate even if an input DC offset of 30 mV. The differential output swing is 1.2 V
pp
. The simulated 3 dB bandwidth is higher than 15 MHz and the gain error is less than 0.7 dB with capacitive loads of 2 pF. The PGA consumes only 4mW from 1.8 V supply. The chip area is 1.50×0.80 mm
²
.