A novel CMOS Charge Pump with high performance for phase-locked loops synthesizer

A novel Charge Pump (CP) circuit with high performance is introduced in this paper. A rail-to-rail operational amplifier is used to enable the CP charge and discharge currents to be match well in a wide output voltage range. A unity-gain amplifier is adopted to eliminate the current sharing problem. Besides, the high initial charge current shortens the settling time of charge pump phase-locked-loops (CPPLLs). The proposed CP designed and realized in 0.18µm CMOS process. The test results show that the current mismatch rate can be less than 0.5% in the output voltage range of 0.23V to 1.72V, with the charge pump current of 100µA and the precharging current of 109µA. The average power consumption of the charge pump in the locked condition is around 0.57mW under 1.8V supply voltage.