By Topic

A novel CMOS Charge Pump with high performance for phase-locked loops synthesizer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shuangshuang Zheng ; Inst. of RF & OE ICs, Southeast Univ., Nanjing, China ; Zhiqun Li

A novel Charge Pump (CP) circuit with high performance is introduced in this paper. A rail-to-rail operational amplifier is used to enable the CP charge and discharge currents to be match well in a wide output voltage range. A unity-gain amplifier is adopted to eliminate the current sharing problem. Besides, the high initial charge current shortens the settling time of charge pump phase-locked-loops (CPPLLs). The proposed CP designed and realized in 0.18μm CMOS process. The test results show that the current mismatch rate can be less than 0.5% in the output voltage range of 0.23V to 1.72V, with the charge pump current of 100μA and the precharging current of 109μA. The average power consumption of the charge pump in the locked condition is around 0.57mW under 1.8V supply voltage.

Published in:

Communication Technology (ICCT), 2011 IEEE 13th International Conference on

Date of Conference:

25-28 Sept. 2011