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A 9.95–11.5Gb/s full rate CDR with jitter attenuation PLL in 65-nm CMOS technology

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2 Author(s)
Xuehui Chen ; Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China ; Yingmei Chen

A PLL based clock and data recovery (CDR) circuit aided with jitter attenuation PLL using 65-nm CMOS technology is presented in this paper. The CDR employs a dual-loop architecture where the frequency-locked loop acts as an acquisition aid to the phase-locked loop. The two loops share the charge-pump (CP), the LC voltage-controlled oscillator (VCO) and the loop filter through a multiplexer (MUX) and a lock detector (LD). An additional jitter attenuation PLL is used to simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network (ITU-T OTN). The simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17ps and is 2.3ps respectively. The core of the whole chip consumes 72mA current from a 1.0V supply.

Published in:

Communication Technology (ICCT), 2011 IEEE 13th International Conference on

Date of Conference:

25-28 Sept. 2011

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