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Area-Power Efficient Modulo 2^{n}-1 and Modulo 2^{n}+1 Multipliers for {2^{n}-1, 2^{n}, 2^{n}+1} Based RNS

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2 Author(s)
Muralidharan, R. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore ; Chip-Hong Chang

Residue Number System (RNS) is often adopted to implement long and repetitive multiplications of cryptographic and signal processing algorithms. To sustain the competitive advantages of RNS over two's complement system in pervasive computing platforms, the hardware cost of parallel modulo arithmetic operations must be lowered. In this paper, new low power and low area modulo multipliers for the well-established {2n - 1, 2n, 2n + 1} based RNS are proposed. The proposed modulo 2n-1 and modulo 2n + 1 multipliers are based on the radix-8 Booth encoding technique. The requisite hard multiples in the critical path are generated by fast customized parallel-prefix adders. In the proposed modulo 2n - 1 multiplier, the number of partial products is lowered to ⌊n/3⌋ + 1, which is around 33% reduction over radix-4 Booth encoded multiplier for n = 32-64 . For modulo 2n + 1 multiplication, the aggregate bias due to the hard multiple and the modulo-reduced partial product generations is composed of multiplier-dependent dynamic bias and multiplier-independent static bias. Both biases have been reduced by properties of modulo 2n + 1 arithmetic and merged into only three n-bit words. Consequently, the total number of partial products in the proposed modulo 2n + 1 multiplier is given by ⌊n/3⌋ + 6, which is 11% and 35% reduction over radix-4 Booth encoded multiplier for n = 32 and 64, respectively. From synthesis results for {2n - 1, 2n, 2n + 1} based RNS multipliers constructed from different modulo 2n - 1 and modulo 2n + 1 multipliers, our proposed modulo multipliers save 4%-40% and 24%-34% area as well as 21%-40% and 7%-19% total power dissipation over radix-4 Booth encoded and non-encoded modulo multipliers, respectively. These results are well correlated with th- theoretical estimation based on the normalized area model.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 10 )

Date of Publication:

Oct. 2012

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