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A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping \Delta \Sigma TDC

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4 Author(s)
Dong-Woo Jee ; Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol. (POSTECH), Pohang, South Korea ; Young-Hun Seo ; Hong-June Park ; Jae-Yoon Sim

This paper presents a low-power noise-shaping ΔΣ time-to-digital converter (TDC) and its application to a fractional-N digital PLL. With a simple structure of single-delay-stage Δ modulator followed by a charge pump based Σ modulator, a wide range of TDC input is converted to ΔΣ modulated single bit stream without loss of signal information. The ΔΣ architecture of TDC effectively improves the conversion performance of linearity and resolution while handling a large input range due to the operation of the dual-modulus divider. In addition, with a downscaling of the amount of the single delay in Δ modulator, the signal and noise transfer characteristics of TDC can be profiled to suppress the out-band noises at the input to the loop filter, resulting in easy filtering without any extra noise cancelling scheme. The DPLL is fabricated with a 0.13 μm CMOS technology. With a loop bandwidth of 1 MHz, DPLL shows an in-band phase noise of - 107 dBc/Hz at 500 kHz offset and an out-of-band phase noise of -118.5 dBc/Hz at 3 MHz offset. The TDC consumes 1 mA.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 4 )

Date of Publication:

April 2012

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