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This paper presents a two-stage modulator for low noise and low power design. The modulator is driven by LO and 2LO; by rejecting noise from the LO path, the modulator achieves a noise floor of -161dBc/Hz at an offset frequency of 40MHz. The modulator also enables the use of a low power injection locked frequency divider (ILFD) to generate quadrature LO. Supplied by 1.2V, the whole circuit consumes only 7.6mA. The modulator is designed in a 65nm CMOS process.
Published in:
ASIC (ASICON), 2011 IEEE 9th International Conference on
Date of Conference: 25-28 Oct. 2011
- Page(s):
- 590 - 593
- ISSN :
- 2162-7541
- E-ISBN :
- 978-1-61284-191-5
- Print ISBN:
- 978-1-61284-192-2
- INSPEC Accession Number:
- 12575960
- Conference Location :
- Xiamen
- Digital Object Identifier :
- 10.1109/ASICON.2011.6157274
- Product Type:
- Conference Publications
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