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A 10 bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 65nm CMOS technology to be embedded in multi-standard wireless transmitters. The proposed block meets the specifications of GSM, TD-SCDMA and WCDMA by digitally adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. As result, the power consumption is optimized according to the operation mode and is 2.8mW in GSM and TD-SCDMA modes, 3.6mW in WCDMA mode. For all considered standards, the SFDR is larger than 75dB, which satisfies all specifications of the standard mentioned above.
ASIC (ASICON), 2011 IEEE 9th International Conference on
Date of Conference: 25-28 Oct. 2011