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A low power 1V 10-bit 100MS/s successive approximation register (SAR) analog-to-digital (ADC) converter is presented. The use of top-plate-sample switching procedure and split capacitive array dramatically reduces total capacitance and saves switching energy. As small total capacitance and split structure together make capacitive array highly sensitive to parasitic capacitance, its layout becomes the key of the ADC. High sampling rate leads to ultra-high logic control clock frequency, so a variable self-timed clock generator is implemented and logical optimization to improve conversion speed is done inside. Special cares are taken to prevent charge leakage caused by 65nm GP process from ruining the dynamic performance. The prototype was fabricated in a 65nm 1P9M GP CMOS technology. Post simulation results show a peak SNDR of 58.364dB and 1.6mW total power consumption with a figure of merit (FOM) of 24fJ/conversion-step.