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A novel approach based on state space equation is developed that yields a log-domain CMOS current-mode filter design methodology. Based on this methodology, a practical second-order filter is realized. In the design, most transistors are biased in sub-threshold region. This characteristic leads to the advantages of low voltage and low power. Moreover, the filter has different gain (0dB, -5dB) for the special frequency channel and its bandwidth can be accordingly adapted through the capacitors or the tuning currents. These results demonstrate that the proposed methodology is useful to the current-mode filter design. The second-order filter (1.4 V, 15 μW) is presented in the standard 0.35-μm technology aiming for some extremely low-power and low-voltage applications such as the hearing aid ASIC where the step gain is required to implement. Finally, the high-order filter design through the proposed methodology is also discussed.