By Topic

Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Meng-Fan Chang ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Pi-Feng Chiu ; Wei-Cheng Wu ; Ching-Hao Chuang
more authors

Low power 3D-IC is well-suited to mobile systems; however, it poses a number of challenges associated with thermal stress, particularly in designs with many stacked layers. The use of a low supply voltage (VDD) and power-down mode help to reduce the power consumption of 3D-ICs, while alleviating aging and thermal effects. These solutions require low-voltage memory and power-down circuitry. Memristor-based logic provides good state retention and restore for power-down operation, and resistive RAM (ReRAM) uses a lower write voltage than conventional Flash memory. This paper reviews design challenges associated with low-voltage SRAM, memristor logic, and ReRAM. We also propose a novel scheme involving homogeneous memory with heterogeneous VDD (HMHV) to further reduce the power consumption of 3D-ICs comprising multiple memory layers.

Published in:

ASIC (ASICON), 2011 IEEE 9th International Conference on

Date of Conference:

25-28 Oct. 2011