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This paper proposes a video processing SoC for Flat Panel Displays and describes the employed video processing algorithms. Three key techniques integrated in the proposed chip are introduced, including spatio-temporal adaptive TV decoder, square-nonlinear interpolation scaler and efficient memory controller. The overall video processing architecture is fabricated at 0.18um CMOS technology node, and the IC is extensively evaluated in a prototype HDTV Set. The proposed SoC chip can well supports both SDTV and HDTV signals, while providing high quality images.
ASIC (ASICON), 2011 IEEE 9th International Conference on
Date of Conference: 25-28 Oct. 2011