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A CMOS low-dropout (LDO) regulator with an output voltage of 1.8 V and a load current up to 100 mA is presented. By introducing an EA loop uses nested Miller compensation, with a differentiator and a comparator enhancement loops to improve the transient response, this LDO achieves full-load stability without off-chip capacitor, and features high transient and frequency performance. Simulation results show that the LDO output voltage varies within 115 mV and settles within 37 μs during line and load transient. It also provides -72 dB power supply rejection (PSR) at 1 kHz.