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Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU

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5 Author(s)
Minh Thien Trieu ; Renesas Design Vietnam Co. Ltd., Ho Chi Minh City, Vietnam ; Huong Thien Hoang ; Phong The Vo ; Hung Bao Vo
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We have applied thoroughly clock gating technique to the SH-4A FPU (Floating Point Unit) core [1] while still keeping it co-operates with CPU core. As a result, 97% flip-flops in FPU is gated. And the power consumption is saved up to 78.11% in FPU, corresponding to 17.02% power consumption reducing of total CPU and FPU core in Dhrystone benchmark. This paper introduces such approach in which the clock is controlled thoroughly and provided to FPU only when the FPU instruction is under-processing.

Published in:

ASIC (ASICON), 2011 IEEE 9th International Conference on

Date of Conference:

25-28 Oct. 2011