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The design and measurement results of a multi-channel power scalable 10-bit digitizer ASIC developed for the luminosity detector at the future linear colliders (ILC/CLIC) are discussed. The 8 channel prototype with different modes of output data serialization was designed and fabricated in a 0.35 μm CMOS technology. The ASIC works for sampling rates from about 10 kS/s to 25 MS/s (50 MS/s in single channel mode) allowing linear scaling of ADCs and serializer power consumption (0.8 mW/MS/s ADC core, 1.2 mW/MS/s total per channel). A wide spectrum of static and dynamic measurements confirm very good ADC resolution (ENOB = 9.7 bits), excellent channel uniformity and negligible crosstalk. To profit from non-continuous detector operation in linear collider experiments and to save power consumption, fast periodic power pulsing is implemented.