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A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass \Sigma \Delta ADC in 0.13 \mu m CMOS

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5 Author(s)
Gupta, S. ; Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA ; Gangopadhyay, D. ; Lakdawala, H. ; Rudell, J.C.
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A reconfigurable bandpass continuous-time ΣΔ RF ADC tunable over the 0.8-2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phase-locked loop (QPLL) allows quadrature phase synchronization between a raised-cosine DAC and a quantizer. Implemented in 0.13 μm CMOS the fully-integrated prototype achieves SNDR values of 50 dB, 46 dB, and 40 dB over a 1 MHz bandwidth at 796.5 MHz, 1.001 GHz and 1.924 GHz carrier frequencies, respectively, with a total power consumption of 41 mW. The measured phase noise of the QPLL is -113 dBc/Hz at an offset frequency of 1 MHz and the reference spur is - 74.5 dBc. The RMS period jitter is 1.38 ps at 3.2 GHz.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 5 )