A new hardware architecture for H.264 intra prediction frame processing

This paper presents a hardware architecture for H.264 intra prediction frame processing. This design reuse some modules according to the common parts of luma 16×16 prediction and chroma 8×8 prediction in architecture and algorithm. Thereby reduces the area of chip and cost, and enhances its market competition. The parallel pipeline is also adopted to enhance the encode efficiency. The top-down design method is adopted in this design. In the beginning the system architecture and C model are designed. Then we implemented the architecture by Verilog HDL. After the ASIC synthesis, which is based on Chartered 0.13μm technology library, it can run 1080P@30 under the clock frequency 102M with 386.46K logic gates. The result of simulation and synthesis show that the timing and area requirement of design are both capable for 1080P@30fps HD applications.