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Performance study of monolithic pixel detectors fabricated with FD-SOI technology

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6 Author(s)
Toshinobu Miyoshi ; Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK), 1-1, Oho, Tsukuba, Ibaraki 305-0801 Japan ; Yasuo Arai ; Ryo Ichimiya ; Yukiko Ikemoto
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We are developing monolithic pixel detectors with a 0.2 μm CMOS, fully-depleted silicon-on-insulator (SOI) technology. The substrate is high-resistivity silicon and works as a radiation sensor having p-n junctions. The SOI layer is a 40 nm thick silicon, where readout electronics is implemented. There is a buried oxide (BOX) layer between these silicon layers. We have already done several Multi Project Wafer (MPW) runs by gathering many pixel designs into a photo mask set, and as the results, several types of integration type pixel detectors (INTPIX) were fabricated. In this document, the design concept and performance in some of INTPIX detectors are described.

Published in:

Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE

Date of Conference:

23-29 Oct. 2011