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A new FPGA-TDC design implemented on a Virtex-4 FPGA is presented. The motivation of our work was to find the best possible time resolution that can be achieved on this type of FPGA. Since other implementations on this FPGA type have been published we have a good basis for a comparison. The new design is an improved version of our previous 10 ps RMS TDC design  that uses dedicated carry-chains for time interpolation purposes and is able to perform two time-measurements in a single carry-chain per hit. In the new design multiple (>;2) measurements can be made in a single chain per hit reaching a time resolution of ~4 ps RMS between two channels.