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Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array

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3 Author(s)
Chul-Moon Jung ; Sch. of Electr. Eng., Kookmin Univ., Seoul, South Korea ; Jun-Myung Choi ; Kyeong-Sik Min

In this paper, a new two-step write scheme is proposed to minimize sneak-path leakage in complementary memristor (CM) array, where no selection device is needed. When R RESET/R SET = 100, the new two-step write scheme can increase the array size of CMs 10 times larger than the conventional write. If R RESET/R SET is increased to 500, we can increase the passive array size up to 1000 × 1000 with maintaining the read sensing margin lager than 10% of VDD. The two-step write scheme will be very essential in realizing passive cross-point array without any selection device that is known to be the ideal architecture for future 3-D memories.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:11 ,  Issue: 3 )

Date of Publication:

May 2012

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