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New Design of 2 \times VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

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2 Author(s)
Chih-Ting Yeh ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Ming-Dou Ker

A new 2 VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit. The proposed design with an SCR width of 50 can achieve a 6.5-kV human-body-model ESD level, a 300-V machine-model ESD level, and a low standby leakage current of only 103.7 nA at room temperature under the normal circuit operating condition with 1.8 V bias.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 3 )