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A DCO is realized in 0.13 μm CMOS using 4 cores for a 5.6 to 11.5 GHz octave tuning bandwidth to provide the clock for an all digital D/PLL CDR circuit. The DCO is novel in that it can track more than a 130 degree C temperature variation while the CDR maintains an error free lock to data. Each core is directly coupled to a div/2 to produce I/Q signals that a 4:1 MUX combines into a single set of 2.8 to 5.8 GHz quadrature outputs to drive the sine interpolator of the CDR. Locked to maximum data rms jitter, integrated from 1 kHz to 1 GHz is 299 fs @ 9.953 Gb/s (Sonet OC-192) from a DCO phase noise of -116 dBc/Hz at 1 MHz offset. The KDCO gain is 190 ppm/bit with less than 2:1 variation over the full bandwidth. The combined DCO, divide by 2 and MUX current is 14 mA to 37 mA on a 1.2 V regulated supply at 25°C.