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A Low Power Inductorless LNA With Double {\rm G} _{\rm m} Enhancement in 130 nm CMOS

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3 Author(s)
Belmas, F. ; LETI, CEA, Grenoble, France ; Hameau, F. ; Fournier, J.

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several gm-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic gm of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP3 is -12 dBm for an input compression point of -21 dBm.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 5 )