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Active leakage is transient, which can be suppressed by design techniques such as dual-Vt. Active-mode power-gating (AMPG) can further reduce active leakage by power-gating groups of gates that perform computations with results that are not loaded due to clock-gating. AMPG involves several challenges; the grouping of gates must take circuit timing into account, and current switches need to be sized to preserve power network integrity as well as circuit timing. We propose solutions to these problems in the content of the entire process of synthesizing AMPG circuits. The physical design of AMPG circuits is also difficult due to the large number of virtual ground rails that must be mutually isolated. We address these issues by integrating placement with power network synthesis. Experiments on several test circuits implemented in 45-nm technology demonstrate the effectiveness of AMPG in the circuits that we synthesized, in terms of power consumption, area, wirelength, and timing.