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Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer Forward Equalizer

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3 Author(s)
Nattapol Sitthimahachaikul ; Solid-State Circuits Research Laboratory, Department of Electrical and Computer Engineering, University of California at Davis, Davis, CA, USA ; Lakshmi P. Rao ; Paul J. Hurst

In an analog discrete-time circular buffer forward equalizer (FE), finite bandwidth in the sample-and-hold (S/H) circuit can introduce significant intersymbol interference (ISI) that degrades the FE performance. This brief investigates the effect of the finite S/H bandwidth and presents two methods to equalize the ISI introduced by the finite S/H bandwidth. The first method uses a decision-feedback equalizer (DFE) that has nonuniform delays between its taps. The second method uses a DFE that has uniform delays between its taps, allows more time in the first DFE feedback loop, and requires fewer DFE taps at the expense of additional FE taps. Simulation results show that when the proposed methods equalize a 100-m CAT5 cable and a backplane channel, the signal-to-noise ratio improvement is at least 1 and 0.8 dB, respectively, for bit error rates <; 10-6 .

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:59 ,  Issue: 3 )