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A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines

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15 Author(s)
Ikenaga, Y. ; Renesas Electron. Corp., Kawasaki, Japan ; Nomura, M. ; Suenaga, S. ; Sonohara, H.
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AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to TCRIT than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 4 )

Date of Publication:

April 2012

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