By Topic

Hybrid C V and I V Technique for Separate Extraction of Structure- and Bias-Dependent Parasitic Resistances in a-InGaZnO TFTs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

12 Author(s)
Hagyoul Bae ; Sch. of Electr. Eng., Kookmin Univ., Seoul, South Korea ; Inseok Hur ; Ja Sun Shin ; Daeyoun Yun
more authors

We report a hybrid technique for extraction of structure- and gate-bias-dependent parasitic source/drain (S/D) resistances (RS and RD) in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). In the proposed technique, C- V and I -V measurements are combined for modeling and extraction. As structural dependence, the active-layer thickness TIGZO , the gate length L, and the overlap length Lov between the S/D and the gate are considered in the equivalent circuit for parasitic resistances. We also separated the horizontal component RH considering the transfer resistance RLT depending on the transfer length LT and the channel resistance RCH, as well as the vertical components in the S/D RVS and RVD. We confirmed the proposed technique through a separate extraction of VGS -independent contact resistances (RCS, RCD) from the channel length- and VGS-dependent RLT and RCH.

Published in:

Electron Device Letters, IEEE  (Volume:33 ,  Issue: 4 )