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This paper presents a low-complexity, high-throughput, and configurable multiple-input multiple-output (MIMO) signal detector design solution targeting the emerging Long-Term-Evolution-Advanced (LTE-A) downlink. The detector supports signal detection of multiple MIMO modes, which are spatial-multiplexing (SM), spatial-diversity (SD), and space-division-multiple-access (SDMA). Area-efficiency is achieved by algorithm and architecture co-design where low-complexity, near-maximum-likelihood (ML) detection algorithms are proposed for these three MIMO modes respectively while keeping in mind that the operations can be reused among different modes. A parallel multistage VLSI architecture is accordingly developed that achieves high detection throughput and run-time reconfigurability. To further improve the implementation efficiency, the detector also adopts an orthogonal-real-value-decomposition (ORVD) aided candidate-sharing technology for low-cost partial Euclidean distance calculation and a distributed interference cancelation scheme for a critical path delay reduction. The proposed multi-mode MIMO detector has been designed using a 65-nm CMOS technology with a core area of 0.25 mm2 (the equivalent gate-count is 88.2 K), representing a 22% less hardware-resource use than the state of art in the open literature. Operating at 1.2-V supply with 165-MHz clock, the detector achieves a 1.98 Gb/s throughput when configured to the 4 × 4 64-QAM spatial-multiplexing mode. The corresponding normalized energy consumption is 51.8 pJ per bit detection.