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Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance

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17 Author(s)
Hayashida, T. ; Sch. of Sci. & Technol., Meiji Univ., Kawasaki, Japan ; Endo, K. ; Yongxun Liu ; O'uchi, S.
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We compared the electrical characteristics, including mobility and on -state current Ion, of n+-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights Hfin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length Lg decreases, Ion for devices with tall fins becomes worse, probably due to a high parasitic resistance Rp. Furthermore, Vth variation increased with increasing Hfin due to rough etching of the fin sidewall. Process technologies for reducing Rp and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

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Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 3 )