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An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits

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3 Author(s)
Yi-Chieh Huang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Ping-Ying Wang ; Shen-Iuan Liu

An all-digital on-chip jitter tolerance measurement technique for clock/data recovery (CDR) circuits is presented. A 6-Gbps CDR circuit with this proposed technique is realized in a 90-nm CMOS process. The measured jitter tolerance by using the testing equipment and the proposed technique correlate within 13 % in the frequency range of 178 kHz ~ 11.3 MHz. The measured peak-to-peak data and clock jitters are 15.56 and 13.3 ps. The power of the CDR circuit is 44.4 mW at a supply voltage of 1.2 V.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 3 )