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A real-time adaptive digital predistortion system (RT-ADPD) for power amplifier linearization is described in this paper, featuring fast closed-loop adaptation to provide robust linearity across quickly shifting power amplifier (PA) operating conditions. The RT-ADPD system requirements, architecture, and its design methodology are analyzed in detail, with particular emphasis on the optimization of the feedback loop convergence speed and stability. A novel, compact algorithm to achieve rapid adaptation of the predistortion lookup tables, without any prior knowledge of the PA distortion characteristics, is introduced. A prototype of the RT-ADPD system is implemented using a field-programmable gate array (FPGA), and it is experimentally exploited to linearize a handset WCDMA PA module. Due to the linearization action, the PA maximum modulated output power is increased by 1.9 dB, to 30.9 dBm, and its power-added efficiency by 9%, to 48.5%, still maintaining a -40-dB ACPR at a 5-MHz offset. In addition, a true closed-loop adaptation ensures excellent PA linearity under load mismatch and other environmental variations. Indeed, ACPR is improved by up to 15 dB, below -47 dB, under 2:1 VSWR at 28 dBm. Remarkably fast adaptation speed is also demonstrated, as adequate signal fidelity is achieved within a ~50-μs time frame.