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The demand of ultralow-power circuits has significantly increased in the last few years. Owing to its great potential in energy savings, the use of supply voltage near or below the transistors' threshold voltages has gained particular attention. Designing these kinds of circuits is still a challenge, particularly when latest advanced process technologies are employed. This brief proposes novel analytical delay models for CMOS circuits running in the subthreshold regime. The delay models proposed here take the effects of the process variability and of the transient variation of the transistors' on-current during the switching into account. Owing to this, delays are predicted with accuracy significantly higher than existing accurate delay models. Furthermore, the novel models are also suitable for gates with transistors' stacks.