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Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

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3 Author(s)
Zjajo, A. ; Delft Univ. of Technol., Delft, Netherlands ; Barragan, M.J. ; de Gyvez, J.P.

This paper reports design, efficiency, and measurement results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS circuits. Additionally, to guide the verification process with the information obtained through monitoring, two efficient algorithms based on an expectation-maximization method and adjusted support vector machine classifier are proposed. The monitors and algorithms are evaluated on a prototype 12-bit analog-to-digital converter fabricated in standard single poly six-metal 90-nm CMOS.

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Instrumentation and Measurement, IEEE Transactions on  (Volume:61 ,  Issue: 8 )