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Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardware description language, (VHDL) and Verilog and consequently target it to Complex programmable logic devices (CPLDs) and Field programmable gate arrays (FPGAs). This paper focuses on using VHDL, to design an application specific integrated circuit (ASIC) liquid dispenser controller system while targeting the device independent architecture (Ultra 3700 CPLD series) for synthesis, optimization and fitting to realize the design. The ASIC controller has two bin cans to dispense regular and diet drinks. The system dispenses a drink if the user activates a button for that drink and at least one can is available. A refill signal appears when both bins are empty. Activating a reset signal informs the system that the machine has been refilled and the bins are full. The design methodology is presented with other details in the body of this paper.