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Fault-tolerance with dual module redundancy for dynamic reconfigurable FPGAs

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4 Author(s)
Qi Zhong Zhou ; Sch. of Autom. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China ; Jing Chen Nan ; Yong Le Xie ; Shu Yan Jiang

Aiming at the reduction of the effects of single event upsets (SEUs) which must be considered in Space applications of Field Programmable Gate Array (FPGA), a novel dependable dual module redundancy (DMR) system based on dynamic configurable FPGAs is presented in this paper. The system can not only detect faults but also recovery the circuits effectively. Using dynamic reconfigurable methodology, the system with low hardware redundancy and high resource utilization is achieved successfully. Through adding redundant comparison test unit, the reliability of system is improved. This new approach has been verified through Xilinx Ml403 development platform equipped with Virtex-4 FPGA chip XC4VFX12. Experimental results verified the effectiveness of the methodology proposed in this paper.

Published in:

Applied Superconductivity and Electromagnetic Devices (ASEMD), 2011 International Conference on

Date of Conference:

14-16 Dec. 2011

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