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Performance per power optimum cache architecture for embedded applications, a design space exploration

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3 Author(s)
Alipour, M. ; Dept. of Electr., Comput. & IT Eng., Qazvin Islamic Azad Univ., Qazvin, Iran ; Moshari, K. ; Bagheri, M.R.

In very deep submicron technologies, limiting the growing on-chip power consumption in memories is a major challenge for embedded system designers. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. Power consumption is as important as performance in battery-powered embedded systems and in future, embedded processors are to process more computation-intensive applications with limited power budgets. Therefore, power consumption of theses processors will become more critical. According to the high contribution of memory access power in total power consumption of embedded systems, memory architecture of embedded systems strongly influences the system design objectives. Therefore, the embedded system designer requires a comprehensive design space exploration for memory architecture. In this paper we explore the design space of cache in embedded processors to find out the cache sizes which have the optimum performance/power consumption in embedded applications.

Published in:

Networked Embedded Systems for Enterprise Applications (NESEA), 2011 IEEE 2nd International Conference on

Date of Conference:

8-9 Dec. 2011

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