Referenced Items are not available for this document.
In this paper a single-cycle issue queue circuit architecture that simplifies the wakeup and selection logic is proposed. The micro-architecture and fully static CMOS circuits are presented for a 32-entry queue that issues four instructions per cycle. The instruction-ready signals are divided into groups and processed in parallel to issue the four oldest ready instructions. The complete issue queue and prioritization logic requires 20 inversions, allowing simulated circuit operation at over 4 GHz in a foundry 45 nm SOI fabrication process.
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:21
,
Issue:
2
)
Date of Publication: Feb. 2013
- Page(s):
- 380 - 384
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 13250656
- Digital Object Identifier :
- 10.1109/TVLSI.2012.2184310
- Product Type:
- Journals & Magazines
- Date of Publication :
- 01 February 2012
- Date of Current Version :
- 17 January 2013
- Issue Date :
- Feb. 2013
- Sponsored by :
- IEEE Circuits and Systems Society
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