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Analysis of yield improvement techniques for CNFET-based logic gates

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3 Author(s)
Rehman Ashraf ; Department of Electrical and Computer Engineering, Portland State University, OR, USA ; Malgorzata Chrzanowska-Jeske ; Siva G. Narendra

CNFET is one of the most promising candidates for a building block of post silicon era integrated circuits due to its excellent electronic properties. The presence of unwanted metallic tubes is identified as a major challenge towards building robust CNT based circuits. Metallic tubes negatively impact the performance, power and yield of CNFET-based circuits. Current CNT growth techniques described in the literature show a wide range, from close to 4% to almost 40%, of metallic tubes being initially present in CNFETs. We used Monte Carlo simulation to analyze yield improvement techniques in both cases; (1) when metallic tubes are present in CNFETs, and (2) when they are removed with extra processing techniques proposed by researches. We proposed design-based promising methods for yield improvement. Suggested and analyzed yield-improvement techniques include transistor, gate and circuit level approaches.

Published in:

Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on

Date of Conference:

15-18 Aug. 2011