By Topic

Analysis of yield improvement techniques for CNFET-based logic gates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ashraf, R. ; Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA ; Chrzanowska-Jeske, M. ; Narendra, S.G.

CNFET is one of the most promising candidates for a building block of post silicon era integrated circuits due to its excellent electronic properties. The presence of unwanted metallic tubes is identified as a major challenge towards building robust CNT based circuits. Metallic tubes negatively impact the performance, power and yield of CNFET-based circuits. Current CNT growth techniques described in the literature show a wide range, from close to 4% to almost 40%, of metallic tubes being initially present in CNFETs. We used Monte Carlo simulation to analyze yield improvement techniques in both cases; (1) when metallic tubes are present in CNFETs, and (2) when they are removed with extra processing techniques proposed by researches. We proposed design-based promising methods for yield improvement. Suggested and analyzed yield-improvement techniques include transistor, gate and circuit level approaches.

Published in:

Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on

Date of Conference:

15-18 Aug. 2011