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In this work, we study the interface traps (ITs) induced electrical characteristic and static noise margin (SNM) fluctuations in 16-nm-gate high-κ/metal gate complementary metal-oxide-semiconductor devices and static random asccess memory circuit. Totally random generated device samples with 2D ITs at silicon/HfO2 interface are simulated using an experimentally validated 3D device simulation. Random number and position of ITs and trap's density on fluctuations of threshold voltage, on/off-state current and gate capacitance are explored and compared among process variation effect (PVE), random dopant fluctuation (RDF) and work function fluctuation (WKF). Notably, the position of ITs induces rather different fluctuation in spite of the same number of ITs.
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Date of Conference: 15-18 Aug. 2011