Design of a Moore finite state machine using a novel reversible logic gate, decoder and synchronous up-counter

Reversible logic is an emerging nanotechnology widely being considered as the potential logic design and implementation of nanotechnology and quantum computing with the main goal of reducing physical entropy gain. Recent advances in reversible logic allow for new avenues in the implementation of reversible combinational circuits. Part of this advancement is the design and implementation of a finite state machine. A proposed novel 4*4 RD gate implemented as a 2-to-4 decoder with low delay and cost is presented, and a novel 4*4 R2D gate used in the implementation of a novel n-to-2ⁿ decoder with low cost and delay. A reversible synchronous up-down counter is presented and verified, and a reduced reversible implementation of a JK Flip Flop is implemented in a reduced reversible synchronous up-down counter. This decoder and counter are then utilized in the design of a reversible Moore finite state machine.