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This paper presents different performance metrics for single electron tunneling (SET) based static memory cell design using unique negative differential conductance (NDC), with emphasis on power optimization. The read/write operations for the memory cell are briefly discussed. All simulations are conducted using the Monte Carlo method from SIMON tools.
Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on
Date of Conference: 15-18 Aug. 2011