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Overview on ATE Test and Debugging Methods for Asynchronous Circuits

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4 Author(s)
Christoph Wolf ; IHP, Frankfurt (Oder), Germany ; Steffen Zeidler ; Milos Krstic ; Rolf Kraemer

Due to mature design tools and proven flows for design and test the majority of today's circuits are synchronous. Increasingly complex designs pose major problems though with respect to clock tree design, interfaces running at different frequencies, peak current consumption and electromagnetic interference. The asynchronous design style promises advantages in these areas but is not widely accepted, mainly due to the lack of design tool support and testability issues. This paper summarizes the problems regarding the test of asynchronous designs as well as existing test methodologies and presents our strategy to increase testability of this kind of devices.

Published in:

2011 12th International Workshop on Microprocessor Test and Verification

Date of Conference:

5-7 Dec. 2011