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Notice of Violation of IEEE Publication Principles
Efficient RTL design of SoCWire BUS protocol

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3 Author(s)
Kumar, R. ; Dept. of Electron. & Commun., Dr. B. R. Ambedkar Nat. Inst. of Technol. Jalandhar, Jalandhar, India ; Sarin, R.K. ; Singh, S.

Notice of Violation of IEEE Publication Principles

"Efficient RTL Design of SoCWire BUS Protocol"
by Ravi Kumar, R.K. Sarin, and Sarabjeet Singh,
in the Proceedings of the 2011 World Congress on Information and Communication Technologies (WICT), December 2011, pp. 1073-1078

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper contains significant portions of text from the papers cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following articles:

"Advanced System-on-Chip Design with In-Flight Reconfigurable Processing Cores for Space Applications"
by B. Osterloh, H. Michalik, B. Fiethe, and K. Kotarowski
Data Systems In Aerospace (DASIA), Palma de Majorca, May 2008

"SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications"
by B. Osterloh, H. Michalik, B. Fiethe, and K. Kotarowski NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2008), pp. 51-56, Noordwijk, June 2008

"System-on-Chip Wire (SoCWire) User Manual"
by B. Osterloh www.socwire.org. SoCWire V1.0, 22.04.20094.

"SpaceWire Inspired Network-on-Chip Approach for Fault Tolerant System-on-Chip Designs"
by B. Osterloh, H. Michalik,and B. Fiethe, in Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication, IGI Global, April 2010

Configurable System-on-chip (SoC) approach for the Venus Express Monitoring Camera (VMC) has been successfully demonstrated in space. For future space missions e.g. Solar Orbiter, the- demand for high performance onboard processing has drastically increased. To achieve these advanced design goals a Reconfigurable System-on-Chip (RSoC) architecture is proposed supported by an on chip flexible communication architecture. In order to communicate between static (which is running during the whole application runtime and stores all critical interfaces) and dynamic partial reconfiguration we design dedicated Network-on-Chip (NoC) approach called SoCWire. This SoCWire provides guaranteed system qualification with hot-plug ability, high speed point-to-point connection and support of the adaptive macro-pipeline as compared to the Bus Macros which suffers from more area and power consumptions. In this work, we present RTL mode SoCWire Codec for point to point communication. The model operates at maximum operating frequency 491 MHz.

Published in:

Information and Communication Technologies (WICT), 2011 World Congress on

Date of Conference:

11-14 Dec. 2011

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