High speed CMOS charge pump circuit for PLL applications using 90nm CMOS technology

The performance of charge pumps depends heavily on the ability to efficiently generate high voltages on-chip while meeting stringent power and area requirements. The paper presents a High Speed CMOS charge pump circuit for PLL applications using 90nm CMOS technology that operates at 1V. The proposed circuit has simple symmetric structure and provides more stable operation while reducing spurious jump phenomenon. The experimental result shows significant improvement in overcoming the problem of jitter. The output voltage of presented design can be increased up to 1010mV. The functionality of charge pump has been tested at operating based frequency of 1000 MHz.